As semiconductor device technology evolves, there is an ever-present need for shrinking all aspects of semiconductor device sizes. However, design and manufacture of various components of semiconductor devices involves different materials and processes, and accordingly, different components scale differently. For example, while sizes of logic and memory cells on a semiconductor chip shrink rapidly as they evolve into the low nanometer and sub-nanometer scales, it is very challenging to shrink the interconnections between these cells at comparable pace. The interconnections are predominantly made up of metal lines, typically formed by materials such as Copper (Cu). Decreasing the size, in terms of thickness or cross sectional area of these metal lines, leads to various issues.
In a more specific example, with semiconductor device technologies below 10 nm, transistor nodes scale below 10 nm. This imposes limitations on the pitch of the metal lines, as they must scale below ˜30 nm. However, for Cu metal lines formed with conventional dual damascene (DD) processes, it is difficult to scale the pitch of the Cu metal lines below 30 nm. At pitches as low as 30 nm, the resistivity of the Cu metal lines (which is inversely proportional to pitch) is very high and high surface or grain scattering is observed. Moreover, increase in resistivity leads to a higher resistance-capacitance product, referred to as “RC delay” or “RC value.”
A back-end of line (BEOL) refers to integrated circuit fabrication related to interconnections between various circuit elements such as transistors, resistors, capacitors, etc. It is observed in conventional integrated circuit designs that RC delay of Cu metal lines forms a dominant portion of the BEOL critical circuit delay. Accordingly, there is a need to reduce RC delay due to metal interconnections.
As already seen, for reducing pitch of the metal lines with shrinking device sizes, it is difficult to keep the resistance (R) component of the RC delay related to the metal lines from rising. In conventional designs, it is also difficult to reduce the capacitance (C) component of the RC delay. This is because capacitance is directly proportional to the dielectric constant (K), and current technology has reached limits on lowering K values for Cu metal lines and surrounding dielectric materials used for interlayer protection and mechanical stability in integrated circuit designs. Reducing the K values further will weaken the mechanical strength of the dielectric materials and may lead to undesirable effects, such as, low-K delamination, which negatively impacts reliability and mechanical stability of the integrated circuits.
Therefore, there is a need in the art for interconnections with low RC delay values, which also avoid drawbacks related to weakened stability and reliability.